Asymmetrical current steering output driver with compact dimensions

ABSTRACT

A current output circuit with two output nodes connectable to a load and providing a plurality of discretely selectable current output magnitudes is provided. The circuit consists of a current driver attached across the output nodes supplying a particular current and one or more bypass resistors connected in parallel with the output nodes that can be switched between a non-conducting state and a resistive conducting state. When a load is connected across said output nodes, the particular magnitude of current sourced through the load can be selected by switching the state of the bypass resistors. The magnitude of the bypass resistors is preselected to provide several discretely selectable states of output current of substantial equal steps. The current driver can be combined with a current switch to increase the number of output states. Several current drivers with current switches may be provided and the bypass resistors integrated into the current switch itself.

TECHNICAL FIELD

[0001] This invention relates to a current mode output circuit. Moreparticularly, this invention relates to an output circuit with adiscretely variable output current.

BACKGROUND OF THE INVENTION

[0002] One type of data interface uses changes in the magnitude of acurrent to transmit data signals. In the simplest case, one state isrepresented by the presence of a current flow and another by the absenceof current. An output circuit of this type using a switch S to connect acurrent driver through the output nodes to a load R_(L) is shown in FIG.1a.

[0003] Other conventional data interfaces, such as those used in SCSIarchitecture, require a current to be always present on an activeinterface. The direction of current flow indicates whether thetransmitted signal is a logic 0 or a logic 1. A conventional currentsteering output buffer of this type is illustrated in FIG. 1b. Thecircuit contains a current driver which is connected to the output nodesby a current switch. In a first state, switch pair S _(A) is closed,switch pair S_(B) is open, and the current driver contributes a currentI to the total load current. In a second state, switch pair S_(B) isclosed, switch pair S_(A) is open, and the current driver contributes acurrent of −I to the total load current. In conventional systems,current may be turned off by opening both switch pairs S_(A) and S_(B).

[0004] As performance of integrated circuits continues to increase, thelimited number of I/O (input/output) pins demands better utilization.Incorporating an output signal with more than the two conventionaldigital output states over a wire allows the interconnect of the I/O tocarry a larger data bandwidth. Previous attempts to do this have usedsignalling via multiple voltage levels. However, in many circumstances,it is preferable to use current signaling instead. Further, conventionalcircuits generate switching noise at either of the power supply leads asthe amount of power flowing into the output circuit is continuouslychanged to thereby vary the output signal level.

SUMMARY OF THE INVENTION

[0005] According to the present invention, an output buffer is providedthat utilizes current signaling to provide a multi-level data output anddraws a constant amount of current from the power supply regardless ofthe output level, thus reducing switching noise and startup delays. Anoutput buffer circuit according to a first embodiment of the presentinvention has a current driver supplying a current I which isconnectable to a load resistance. The connection may be through acurrent switch. The circuit also has one or more bypass resistors whichcan be switchable connected in parallel with the load resistance ordisconnected from the circuit. When a bypass resistor is switched inparallel with the load resistor, some of the output current is divertedthrough the bypass resistor, thus reducing the current supplied to theload. For N switched bypass resistors, there are 2^(N) possible resistorstate combinations. By choosing appropriate resistance values for thebypass resistors, the current through the load resistor may be varied in2 ^(N) discrete. The number of states may be increased to 2^(N)+1 if acurrent switch which allows the direction of the output current to bereversed or stopped is included in the output circuit. According to theinvention, a zero-current output state is achieved by closing allswitches in the current switch, instead of opening them. In this state,the introduced current flows equally in both directions through the loadand therefore does not contribute a net current even though the givencurrent driver is still sourcing current. Because the effect of acurrent driver on the load current may be eliminated without shuttingoff the current, it is possible to avoid startup delay and noise whichwould be introduced if the current switch were disconnected from thecircuit by opening all the internal switches. Preferably, N bypassresistors are provided having appropriate resistances to provide atleast N equal current steps for each current direction.

[0006] In another embodiment, a plurality of current drivers is providedand connected to the load resistance in parallel. It can be appreciatedthat when both of the current paths in a given current switch are active(e.g., all internal switches in a particular current switch are closed),no net current flow will be introduced into the load. However, theinternal switches will also introduce a resistance in parallel with theload resistor. According to this aspect of the invention, the resistanceof each internal switch is chosen so that when all internal switches areclosed, the current switch provides a preselected effective resistancein parallel with the load which diverts current flow from other (active)current drivers and thereby reduces the current in the load by apredefined discrete amount. The magnitude of each current source and theeffective resistance of the switches in each current switch can bechosen to minimize the number of redundant output states, and thereforemaximize the number of possible output current steps.

[0007] A multiple-state current output circuit according to the presentinvention can be fabricated as an integrated circuit using MOStransistors and located on the same chip as its driving circuitry. Thepresent design allows for compact circuit dimensions when compared withconventional circuits of a similar type.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing and other features of the present invention will bemore readily apparent from the following detailed description anddrawings of illustrative embodiments of the invention in which:

[0009]FIGS. 1a and 1 b are ideal representations of conventional currentoutput circuits;

[0010]FIG. 2 is an ideal representation of an output circuit accordingto a first embodiment of the invention;

[0011]FIGS. 3a and 3 b are graphs of load current for various switchstates and resistance values in the circuit of FIG. 2;

[0012]FIG. 4 is an ideal representation of an output circuit accordingto a second embodiment of the invention;

[0013]FIGS. 5a and 5 b are circuit diagrams of switchable bypassresistors according to the invention;

[0014]FIGS. 6a-6 c are ideal representations of an output circuitaccording to a third embodiment of the invention;

[0015]FIGS. 7a- 7 c show circuit diagrams of the preferredimplementation of the circuits of FIGS. 6a according to one specificimplementation of this particular embodiment; and

[0016]FIG. 8 is a graph of the output currents for the circuit of FIGS.7a-7 c with a varying transistor bias voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017]FIG. 2 is an ideal representation of an output circuit accordingto a first embodiment of the invention having two output nodes 20 and 22and a current driver comprised of current source 24 which supplies acurrent I. The output driver is connected to a receiving unit, indicatedas load resistance R_(L) 26, through the output nodes 20, 22. Accordingto the invention, one or more bypass resistors R₁ through R_(N) areswitchable connected in parallel with the load resistance R_(L), e.g.,by means of switches S₁ through S_(N), to form switchable bypassresistor assemblies. By closing one or more of the switches, the currentI_(L) driven through the load 26 can be varied in discrete steps betweena maximum current of I and a minimum current ofI_(L)=I*R_(E)/(R_(L)+R_(E)), where R_(E) is the equivalent parallelresistance introduced when all N bypass resistors are conducting.Advantageously, the net current flow from the current driver 24 remainsconstant at I, even as the load current is changed. This reducestransient switching effects on the current driver and allows for highswitching speeds and low output noise.

[0018] The value of bypass resistors R₁ through R_(N) can be defined interms of the expected load resistance R_(L) and preferably are chosen sothat the output buffer can source current in at least N+1 substantiallyequal output current steps. For example, if N=3, the value of the bypassresistors can be selected to provide, for example, four equal outputcurrent steps of magnitude I, 3/4I, 1/2I, and 1/4I. Depending on variousdesign considerations, such as switching speed, device area, etc.,several switching configurations may be used. In a “single-switch”configuration, four equal steps are achieved by switching only onebypass resistor at a time to a conducting state. In tabular form, thisparticular “single-switch” arrangement is summarized as: S₁ S₂ S₃ I_(L)0 0 0 I 1 0 0 ¾ I 0 1 0 ½ I 0 0 1 ¼ I

[0019] where a “1” indicates that a switch is closed, i.e., the bypassresistor is conducting, and a “0” indicates that the switch is open,i.e., the bypass resistor is non-conducting. To achieve this result, thevalues of the bypass resistors are:

R₁=3R_(L) R₂=R_(L) R₃=1/3R_(L)

[0020] In the general case of M equal output current steps separated byI/M in a “single-switch” configuration, N=M−1 switched bypass resistorsare provided. The values of each switched bypass resistor R_(n) and theresulting load current I_(L)when only that particular resistor isconducting (only switch S_(n) is closed) is given by equation 1:$\begin{matrix}{R_{n},{{I_{L{(n)}}\int_{n = 1}^{N}} = {\frac{N - n + 1}{n}R_{L}}},{\frac{N - n + 1}{N + 1}I}} & \text{(Equ. 1)}\end{matrix}$

[0021] Thus, for 8 equal states, N=7 and the values of bypass resistorsR₁ to R₇ is:

7/1R_(L) 6/2R_(L) 5/3R_(L) 4/4R_(L) 3/5R_(L) 2/6R_(L) 1/7R_(L)

[0022] The output current when only bypass resistor R_(n) is conductingfor n=1−7 is:

7/8I 6/8I 5/8I 4/8I 3/8I 2/8I 1/8I

[0023] (The final state, output of I, is achieved when all resistors arenon-conducting, i.e., no switches are closed).

[0024] Other configurations may also be used to achieve equal outputcurrent steps. For example, in a “cumulative parallel” configuration,the switches are closed successively, adding more than one bypassresistor in parallel with the load resistor at a time. The four statesachieved in this configuration where N=3 may be represented as: S₁ S₂ S₃I_(L) 0 0 0 I 1 0 0 ¾ I 1 1 0 ½ I 1 1 1 ¼ I

[0025] To achieve this result, the values of the bypass resistors areconfigured as:

R₁=3R_(L) R₂=3/2R_(L) R₃=1/2R_(L)

[0026] It can be appreciated that even though the resistor values may beoptimized to provide equal current steps for certain switchconfigurations, such as the single-switch or cumulative-parallelconfigurations discussed above, all of the 2^(N) switch combinations canbe utilized if desired. FIG. 3a is a graph of the output current I_(L)for each of the eight possible output states using the values of thesingle-switch configuration example. FIG. 3b is a similar graph for theresistor values of the cumulative-parallel configuration example. Ineach graph, the points at equal steps of 1/4I are indicated by a box. Inboth graphs, it can be seen that when the bypass resistor values areconfigured to achieve four equal steps as discussed above, the minimumseparation between current points diminishes as more resistors areswitched into place. Accordingly, the number of additional detectablestates may be limited by noise concerns. Therefore, it would beadvantageous to introduce additional states without reducing the currentpoint separation.

[0027]FIG. 4 shows the output driver 10 according to a second embodimentof the invention. In this invention, a current switch 15 is integratedwith the driver of FIG. 2. Current switch 15 connects the currentdriver, here formed of matched current source 24 and current sink 25, tothe output nodes 20, 22 via internal switch pairs S_(A) and S_(B).Although all four internal switches in a given current switch can beindependently controlled, for purposes of this discussion, switcheswhich are normally closed together are given the same designation andare discussed in pairs. When switch pair S_(A) is open and switch pairS_(B) is closed, current flows out from node 22 through the load 26 andback into node 20. When switch pair S_(A) is closed and switch pairS_(B) is open, current flows through the load in the opposite direction.

[0028] By including a current switch in the output circuit, the numberof available current output states is doubled. In addition, azero-current state can be achieved by opening or closing the internalswitch pairs S_(A) and S_(B) in unison. Thus, for example, by usingthree switched bypass resistors configured as discussed above combinedwith a current switch as shown, eight primary output current states atsteps of 1/4I can be achieved. An additional, ninth zero-current statecan also be achieved by opening or closing both switch pairs S_(A) andS_(B) together.

[0029] Accordingly, in this example, a three-bit digital output may beencoded in a single current signal. Advantageously, the circuitaccording to the present invention provides a wide and uniformseparation between each of the current levels. This results in a robustoutput signal which can absorb a significant degree of noise, up to+/−1/8I, and still provide extractable data.

[0030] In the preferred embodiment, the conducting or non-conductingstate of the bypass resistors (here shown as the state of resistorswitches S₁ to S₃) and the state of current switch pairs S_(A) and S_(B)is controlled by conventional logic circuitry which converts a three-bitoutput value into appropriate control signal combinations. If the bypassresistors R₁ to R₃ are configured to be used in a single-switcharrangement, as discussed above for example, the nine output logicstates may be encoded as follows: Output S₁ S₂ S₃ SA SB I_(L) 111 0 0 01 0 +I 110 1 0 0 1 0 +¾ I 101 0 1 0 1 0 +½ I 100 0 0 1 1 0 +¼ I — — — —both 1/0 0 011 0 0 1 0 1 −¼ I 010 0 1 0 0 1 −½ I 001 1 0 0 0 1 −¾ I 0000 0 0 0 1 −I

[0031] A similar state table can easily be configured for theparallel-cumulative example discussed above. Appropriate logic circuitrycan be designed directly from state tables such as this as is well knownin the art.

[0032]FIGS. 5a and 5 b show preferred structures for implementing theswitchable bypass resistors. In FIG. 5a, a switchable bypass resistor isimplemented as two series-connected MOS transistors 100, 102 driven by areference voltage Vref 103 which is adjusted tso that the transistors100, 102 are either non-conducting or resistively conducting.Preferably, a capacitor 104 is connected from node 105 (the junction oftransistors 100, 102) to ground. Capacitor 104 serves to provide an ACground for common mode signals which may be induced in the circuit.Although only one MOS transistor is necessary, preferably two are usedin combination with a capacitor because it is beneficial to have an ACground at the center point.

[0033] In this embodiment, when the driving voltage Vref 103 is belowthe turn-on voltage for transistors 100, 102, the transistors arenon-conducting. When a voltage greater the turn-on voltage (for NMOStransistors) is applied to the gates of transistors 100, 102, theyconduct and have a specific resistance dependant on the geometry of eachtransistor and the applied voltage gate Vref 103. The proper biasingvoltage to apply to a given MOS transistor so as to set it to aparticular predefined resistance can be generated using feedbackcircuits. One such feedback circuit is described below.

[0034] According to another aspect of the invention, the output circuitis fabricated as an integrated circuit on a single chip so that alltransistors in the circuit are exposed to the same fabricationconditions. A single bias voltage Vref may then be used for all of theswitched bypass resistors implemented as MOS transistors by scalingvarious transistors relative to a “master” transistor that is biased toa known resistance. For example, if transistor 100 biased with a voltageV has a resistance R, a resistance of 2R may be achieved by applying thesame biasing voltage V to a transistor with a channel width half that oftransistor 100 and having the same length. Similarly, a resistance of0.5R may be achieved by applying voltage V to a transistor having achannel twice as wide but the same length as transistor 100. Because allthe transistors are fabricated with identical process conditions, errorsintroduced during fabrication cancel out.

[0035]FIG. 5b shows an alternative embodiment for implementing aswitched bypass resistor. In this embodiment, two resistors 116, 118 areconnected in series with two MOS transistors 110, 112. The transistorsare driven by a biasing voltage Vbias 114. Preferably, a capacitor 120is connected between the junction of the transistors 110, 112 (node 119)and ground. As above, in the “off” condition, the transistors 110; 112are non-conducting. However, in the “on” state, the transistors aredriven with a biasing voltage sufficient to place them in a saturatedstate so that their internal resistance is small when compared withresistors 116, 118. In this embodiment, the transistors are preferablydriven using digital signals of appropriate magnitudes. The resistorscan be fabricated using any appropriate technique and can be on-oroff-chip passive devices, or even appropriately biased transistors.

[0036]FIG. 6a is an ideal representation of a third embodiment of theinvention. As shown, current output circuit 50 consists of a pluralityof current drivers, in this example drivers 56, 57, 58, which areconnected in parallel to output nodes 52, 54, and thereby to a loadresistor R_(L) 26, representing an attached receiving device. Each ofthe current drivers preferably includes a matched current source andsink connected to the output nodes by a current switch. Driver 56includes current source and sink 60, 62 which provide a current I₁through current switch 64 having switch pairs S₁ and S₂. Driver 57includes current source and sink 66, 68 which provide current I₂ throughcurrent switch 70 having switch pairs S₃ and S₄. Driver 58 includescurrent source and sink 72, 74 which provide current I₃ through currentswitch 76 having switch pairs S₅ and S₆.

[0037] According to this aspect of the invention, the output currentI_(L) through load 26 may be varied by selectively providing variouscombinations of currents _(I1) to _(I3), in either direction, via thecurrent drivers 56, 57, 58. Further according to the invention, theresistance of switch pairs S₁- S₆, when conducting, is set to variouspredefined values. Each switch thus functions as a switchable bypassresistor as discussed above. In addition, all of the internal switchesin a given current switch are configured so that the net resistance foreach path between the given current source and current sink isequivalent. This ensures that when all internal switches in a givencurrent switch are closed, half the switched current flows in onedirection through the load and half flows in the other direction.

[0038] In this state, no net current is introduced into the load fromthe particular current driver and therefore, the particular switchedcurrent can be ignored. According to the invention, however, because theclosed internal switches have a predefined resistance, closing bothswitch pairs also introduces a predetermined effective resistance inparallel with the load. This diverts current flow from other currentdrivers and thereby reduces the current in the load by a particularamount. The resistances of the internal switches and thereby theeffective resistance associated with each current driver is chosen toprovide for a plurality of discretely selectable current levels throughthe load in a manner similar to that discussed above with respect toFIGS. 2-4.

[0039] Each internal switch in a switch pair S can be considered anideal switch in series with a resistor R or a voltage-controlledresistor. For purposes of clarity, when a given switch is open, i.e.,when the resistor is not conducting, only the open-switch portion isshown in the figures. When an internal switch is closed, i.e., theresistor is conducting, it is represented as the equivalent resistance.It can be appreciated that each internal switch in each of the currentswitches 64, 70, 76 can have a different internal resistance subject tothe constraint, in this embodiment, that the two current paths in agiven current switch, i.e., the path through each pair of switches, haveequivalent resistances to allow for a zero net current flow state aspreviously discussed. For purposes of simplicity, it is assumed thateach of the four internal switches comprising a given current switch 64,70, 76 have the same internal resistance, defined as R₆₄, R₇₀, R₇₆,respectively.

[0040]FIG. 6b is an illustration showing the circuit 50 with switchpairs S₁, S₃, and S₅ closed and replaced with their equivalent switchresistances, R₆₄, R₇₀, R₇₆. Because each resistance is introduced inseries between a current source/sink and the load, the internalresistances do not affect the net current flow, only the voltage dropacross the load. Thus, the net current flow I_(L) through load resistorR_(L) is I₁+I₂+I₃. This sum is defined as the maximum output current I.(Analogously, if switch pairs S₂, S₄, and S₆ were closed, the totalcurrent through the load would be −I).

[0041]FIG. 6c is an illustration showing the circuit 50 with switchpairs S₃, and S₅ closed and replaced with their equivalent switchresistances, R₇₀, R₇₆. In addition, current switch 64 has both switchpairs S₁ and S₂ closed and is therefore in a zero net current state.Therefore, current I₁ is not contributing current to the load becausethe effect of switched current I₁ is equal in both directions. Note,however, that the I₁ current is still flowing, and therefore, switchingnoise and start-up delays associated with stopping current flow are notintroduced. The total contributing current flow is I₂+I₃. However, asshown in the figure, the internal switch resistances from current switch64 are now in parallel with the load resistor R_(L). This introduces aparallel aggregate resistance of (R₆₄+R₆₄)¦¦R₆₄+R₆₄)=R₆₄, where“¦¦”signifies a parallel combination. This bypass resistance diverts aportion of the I₂+I₃ current, thereby reducing the output current I_(L).According to the invention, the parallel equivalent resistance (and thuseach internal switch resistance) R₆₄ is chosen to provide a particularoutput current in a manner similar to that discussed above for FIGS.2-5. Preferably, the switchable resistors used in switch pairs S₁-S₆ areimplemented as MOS transistors as shown in FIGS. 5a and 5 b, discussedabove, as are the current drivers 60, 66, and 72, and the referencevoltage circuit which applies the appropriate gate voltage(s).

[0042] In one configuration, for example, I₁=0.1I, I₂ =)0.3I, andI₃=0.6I and the resistances R₆₄, R₇₀, and R₇₆ are set to 2R_(L),2/3R_(L), respectively. When all three current switches 64, 70, and 76are contributing current in the same direction (FIG. 6b), the netcurrent flow is I. When current switch 64 is set to a non-contributingstate as shown in FIG. 6c, current I₁ does not contribute to the loadand a resistance of R₆₄=2R_(L) is placed in parallel with the loadresistance R_(L). Because currents I₂ and I₃ remain contributing, thetotal sourced current is 0.3I+0.6I=0.9I. R_(L) is in parallel with abypass resistance equal to 2R_(L) and so the current sourced to the loadis 0.9I*2R_(L)/R_(L) =R _(L))=0.9I*2/(1+2)=0.6I. Similarly, in the casewhere switch pairs S₁, S₂, S₃, S₄, and S₅ are closed, only the currentdriver 58 is contributing I₃ =)0.6I and the resulting load current is0.2I. Similar calculations can be performed for other current switchstates as well. One group of switch states for this embodiment and theresulting load current is summarized in the following table, where a 1indicates that a switch pair is closed and a 0 indicates that a switchpair is open. S₁ S₂ S₃ S₄ S₅ S₆ I_(L) 1 0 1 0 1 0 I 1 1 1 0 1 0 0.6 I 11 1 1 1 0 0.2 I 1 1 1 1 1 1 0 1 1 1 1 0 1 −0.2 I 1 1 0 1 0 1 −0.4 I 0 10 1 0 1 −I

[0043]FIGS. 7a-7 c show circuit diagrams of a preferred implementationof this particular embodiment, using the selected values from theprevious example. All components except for a single reference resistorare implemented as MOS transistors. All transistors preferably have thesame gate length, most preferably the minimum value supported in a givenfabrication technology, but may have varying gate widths. According toone aspect of the invention, the entire output circuit is fabricated aspart of a single integrated circuit where the current output circuitsare simply scaled versions of each other. In a simple scaling scheme,the lengths of the transistor gates are kept constant, while the widthsof the gates are adjusted to provide the desired relative resistanceand/or current.

[0044] Turning now to FIG. 7a, representative current driver 56 consistsof a current source formed by p-channel MOS transistor 150 biased to agate voltage Pch, and a current sink formed by N-channel MOS transistor152 biased to a gate voltage Nch, which together produce current I₁.Transistors 150 and 152 have gate widths of 70 and 18 microns,respectively, and are connected to output nodes 154, 156 through acurrent switch 64 formed by N-channel transistors 160, 162, 164, and166, having gate widths of 95, 50, 95, and 50 microns respectively. Thegates of transistors 160 and 162 are connected to input voltage IN₁ andtogether correspond to switch pair S₁ shown in FIG. 6a. The gates oftransistors 164 and 166 are connected to input voltage INN₁ and togethercorrespond to switch pair S₂ shown in FIG. 6a. The input gate voltagesIN₁ and INN₁ are set to either turn off the given transistors (i.e.,zero volts), or bias them to a common voltage, Vcom, which places themin a resistive conducting state having the desired resistance.

[0045]FIG. 7b is one embodiment of a voltage reference circuit 168 forgenerating the bias voltages Pch and Nch for transistors 150 and 152.The circuit consists of a current source formed by P-channel transistor170 and a current sink formed by N-channel transistor 172. The currentdriver formed by transistors 170 and 172 is connected to output nodes174, 176 through a current switch formed by N-channel transistors 180,182, 184, and 186, which are connected as shown. The gates oftransistors 180 and 182 are driven by a bias voltage Vcom which placesthem in a resistive conducting state. The particular resistance of theseswitches is set by adjusting the value of Vcom as desired and will bediscussed below. The gates of transistors 184 and 186 are grounded andtherefore, these transistors are non-conducting.

[0046] A reference resistance R_(REF) 188 is connected across nodes 174and 176. Resistor 188 is chosen to have a resistance equal to theexpected load resistance R_(L) 26 which will be connected to the outputbuffer. The geometric dimensions of transistors 170, 172, 180, 182, 184,and 186 correspond symmetrically to transistors 150, 152, 160, 162, 164,and 166 respectively (FIG. 7a). Preferably, corresponding transistorshave the same dimensions. Because the circuits of FIG. 7a and 7 bcorrespond geometrically, it can be appreciated that once the biasvoltages for transistors 170 and 172 are set to provide a specificcurrent through known resistance R_(REF) 188, i.e., a current equal toI₁, these bias voltages can then be applied to corresponding transistorsin output buffer circuits 56 to produce currents with a predefinedmagnitude when driving a load having resistance equal to R_(REF).

[0047] The proper biasing voltages, Pch and Nch, are generated usingfeedback comparators 190 and 192. Comparator 190 is driven by inputvoltage V2 and the voltage at node 174 and its output is used to biastransistor 170. This circuit will adjust the biasing of transistor 170until the sourced current places the voltage at node 174 equal to V2.Similarly, comparator 192 is driven by input voltage V1 and the voltageat node 176 and its output used to bias transistor 172. This circuitwill adjust the bias of transistor 172 until the sunk current places thevoltage at node 176 equal to V1. Since the reference resistance RREF 188is known, the voltage drop across the resistor 188 can be set to providethe desired current, i.e., I=(V2−V1)/R_(REF). For example, with aresistance of 100 Ohms, a set voltage drop between 2.4 and 2 volts wouldresult in a current of 4 milliamps.

[0048] Voltage reference circuits of this type are described in moredetail in commonly assigned U.S. patent application Ser. No. 08/882,827entitled “Low Voltage Differential Swing Interconnect Buffer Circuit,”filed on Jun. 26, 1997, the entire contents of which are herebyincorporated by reference.

[0049]FIG. 7c shows a complete output circuit implementing the specificexample discussed above and using the circuits of FIGS. 7a and 7 b. Asshown, reference circuit 168 generates bias voltages Pch and Nch basedon reference resistor 188 and input voltages V1, V2, and Vcom. In thisexample, voltages V1 and V2 have a difference of several hundredmillivolts, i.e., V1=1.0 volts and V2=1.4 volts. A plurality of outputdrivers are connected in parallel between output nodes 52 and 54. Theoutput circuit 56 shown in FIG. 7b corresponds to the “1x” outputcircuit. Circuits 57 and 58 are scaled versions of circuit 56, where thetransistors have gate widths of 3x and 6x, respectively, of thecorresponding transistors in circuit 56. Accordingly, if circuit 56 isdefined to produce output current I₁=0.1I, circuit 57 will produceI₂=3*I₁=0.3I and circuit 58 will produce output current I₃=6*I₁=0.6I.The switch states of each output driver are controlled by a digitalcontrol circuit 200, which implements, for example, the state tableshown above by providing a zero or ground voltage to a given transistorgate when it is to be non-conducting and providing an output voltageequal to Vcom when a switch is to be in a conducting state. Controlcircuits of this type are well known in the art.

[0050] As mentioned above, varying the biasing voltage for conductingtransistors (i.e., Vcom) results in different output currents becausethe resistance of the transistors is varied. FIG. 8 is a graph ofsimulated output currents for the example circuit discussed above withVcom varied between 2.0 volts and 3.8 volts. As can be seen, resultsgenerally in line with the ideal situation are achieved with a drivingvoltage Vcom of approximately 2.2 volts. Various methods of producingthe appropriate driving voltage are known to those skilled in the artand include, for example, resistive divider circuits, feedback circuits,etc.

[0051] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A current output circuit having first and secondoutput nodes connectable to a load resistance, said circuit comprising:a current driver connected to at least one of said first and secondoutput nodes and supplying a total current I; and at least one bypassresistor connected between said first and second output nodes, eachbypass resistor being switchable between a non-conducting state and aconducting state having a predetermined resistance, the states of saidat least one bypass resistor providing a plurality of discretelyselectable output current states of particular current magnitudesthrough said load when said load is connected to said output nodes. 2.The circuit of claim 1, wherein the value of each predeterminedresistance is such as to provide a plurality of substantially equaloutput current steps between output current states.
 3. The circuit ofclaim 2, comprising N bypass resistors, the predetermined resistance ofsaid bypass resistors relative to the expected load resistance beingsuch as to provide N+1 selectable output current states with currentmagnitudes varying between approximately (1/N+1)*I and I in discretesteps of substantially (1/N+1)*I.
 4. The circuit of claim 1, furthercomprising a current switch connected between said current driver andsaid output nodes so as to control the direction of current flow throughsaid load, when connected.
 5. The circuit of claim 1, wherein each saidbypass resistor comprises an MOS transistor controlled by a voltageappearing at the gate thereof, said MOS transistor being non-conductingwhen the magnitude of said gate voltage is a first voltage and said MOStransistor being conducting and having a predetermined resistance whenthe magnitude of said gate voltage is a second voltage.
 6. The circuitof claim 1, wherein each bypass resistor comprises first and secondseries connected MOS transistors, the gates of said transistors beingconnected to a common reference voltage, said MOS transistors beingnon-conducting when the magnitude of said reference voltage is at afirst voltage, said MOS transistors being conducting and havingpredetermined resistance when the magnitude of said reference voltage isat a second voltage.
 7. The circuit of claim 6, further comprising acapacitor connected to the connection between said first and secondtransistors and to a common ground voltage.
 8. The circuit of claim 1,wherein each bypass resistor comprises a switch in series with aresistor.
 9. The circuit of claim 1, wherein each said bypass resistorcomprises: a first resistor; a first MOS transistor connected in serieswith the first resistor; a second MOS transistor connected in serieswith the first transistor; and a second resistor connected in serieswith the second transistor: the gates of the first and secondtransistors being connected to a common switching voltage, thetransistors being non-conducting when said switching voltage is at afirst voltage, and the transistors being conducting when said switchingvoltage is at a second voltage.
 10. An integrated circuit including acurrent output circuit having first and second output nodes connectableto a load resistance, said current output circuit comprising: a currentdriver connected to at least one of said first and second output nodesand supplying a total current I; and at least one bypass resistorconnected between said first and second output nodes, each bypassresistor being switchable between a non-conducting state and aconducting state having a predetermined resistance, the states of saidat least one bypass resistor providing a plurality of discretelyselectable output current states of particular current magnitudesthrough said load when said load is connected to said output nodes. 11.The circuit of claim 10, wherein the value of each predeterminedresistance is such as to provide a plurality of substantially equaloutput current steps between output current states.
 12. The circuit ofclaim 11, comprising N bypass resistors, the predetermined resistance ofsaid bypass resistors relative to the expected load resistance beingsuch as to provide N+1 selectable output current states with magnitudesvarying between approximately (1/N+1)*I and I in discrete steps ofsubstantially (1/N+1)*I.
 13. The circuit of claim 10, further comprisinga current switch connected between said current driver and said outputnodes so as to control the direction of current flow through said load.14. The circuit of claim 10, wherein each said bypass resistor comprisesa transistor.
 15. The circuit of claim 10, wherein each bypass resistorcomprises an MOS transistor controlled by a signal switchable betweenfirst and second voltage magnitudes, said MOS transistor beingnon-conducting when the magnitude of said signal is at a first voltageand said MOS transistor being conducting and having a predeterminedresistance when the magnitude of said signal is at a second voltage. 16.The circuit of claim 15, wherein a particular MOS transistor in one ofsaid bypass resistors is a scaled version of a corresponding MOStransistor in a second one of said bypass resistors, the controllingsignals for said scaled and corresponding MOS transistors beingswitchable between substantially the same first and second voltages. 17.The circuit of claim 10, wherein each bypass resistor comprises firstand second series connected MOS transistors, the gates of saidtransistors being connected to a common reference voltage, said MOStransistors being non-conducting when the magnitude of said referencevoltage is at a first voltage, said MOS transistors being conducting andhaving a predetermined resistance when the magnitude of said referencevoltage is at a second voltage.
 18. The circuit of claim 17, furthercomprising a capacitor connected to the connection between said firstand second transistors and to a common grounding voltage.
 19. Thecircuit of claim 10, wherein each bypass resistor comprises a switch inseries with a resistor.
 20. The circuit of claim 10, wherein each bypassresistor comprises: a first resistor; a first MOS transistor connectedin series with the first resistor; a second MOS transistor connected inseries with the first transistor; and a second resistor connected inseries with the second transistor; the gates of the first and secondtransistors being connected to a common switching voltage, thetransistors being non-conducting when said switching voltage is at afirst voltage, and the transistors being conducting when said switchingvoltage is at a second voltage.
 21. In an integrated circuit, a currentoutput circuit having first and second output nodes connectable to aload, said output circuit comprising: a plurality of current drivers;and a plurality of current switches, each said current switch connectinga respective current driver to an output node and comprising first andsecond switches forming a first switch pair having a particularresistance when conducting, and third and fourth switches forming asecond switch pair having substantially said particular resistance whenconducting; each said current switch having at least three data states,in the first data state, said first switch pairs being closed and saidsecond switch pairs being open to connect the respective current driverto said output nodes, whereby current flows from said first output nodethrough the load, when connected, and into said second output node; inthe second data state, said first switch pairs being open and saidsecond switch pairs being closed to connect the respective currentdriver to said output nodes, whereby current flows from said secondoutput node through the load, when connected, and into said first outputnode; and in the third data state, said first and second switch pairsbeing closed to thereby introduce a resistance in parallel with saidload, when connected, the net current through said connected load fromsaid respective current driver being substantially zero.
 22. The circuitof claim 21, wherein each of said current drivers supplies a current ofa different magnitude.
 23. The circuit of claim 21, further comprising acontrol circuit receiving digital data as input and providing outputsignals to control the states of said switch pairs in said currentswitches.
 24. The circuit of claim 21, wherein each of said firstthrough fourth switches in said current switches is an MOS transistor.25. The circuit of claim 24, wherein each said MOS transistor has acontrol signal appearing at the gate thereof, said MOS transistor beingnon-conducting when the magnitude of said control signal is a firstvoltage, said MOS transistor being conducting and having a particularpredetermined resistance when said control signal is a second voltage.26. The circuit of claim 25, wherein said MOS transistors forming saidfirst through fourth switches in one of said current switches are scaledversions of corresponding MOS transistors forming first through fourthswitches in a second one of said current switches, each of the controlsignals for said scaled MOS transistors being switchable betweensubstantially the same first and second voltage magnitudes as thecontrol signals for said corresponding MOS transistors.
 27. The circuitof claim 26, further comprising: a control circuit receiving digitaldata as input and providing output signals to control the states of saidswitch pairs in each one of said current switches.
 28. An integratedcircuit including a current output circuit having first and secondoutput nodes connectable to a load, said output circuit comprising aplurality of resistively switched current drivers connected to saidoutput nodes in parallel; each said driver comprising: a current sourceincluding an MOS transistor biased to a source reference voltage; acurrent sink including an MOS transistor biased to a sink referencevoltage; a resistive current switch connecting said current source andsaid current sink to said first and second output nodes, said currentswitch including: a first MOS transistor connected between said currentsource and said first output node; a second MOS transistor connectedbetween said second output node and said current sink; a third MOStransistor connected between said current source and second output node;and a fourth MOS transistor connected between said first output node andsaid current sink; a first control signal connected to the gates of saidfirst and second transistors; a second control signal connected to thegates of said third and fourth transistors; said transistors in each oneof said drivers being scaled versions of corresponding transistors ineach other one of said drivers; said controlled first and secondtransistors being non-conducting when said first control signal is at afirst voltage and being resistively conducting when said first controlsignal is at a second voltage; said controlled third and fourthtransistors being non-conducting when said second control signal is atsubstantially said first voltage and being resistively conducting whensaid second control signal is substantially said second voltage.
 29. Thecircuit of claim 28, further comprising means for generating said sourceand sink reference voltages.
 30. The circuit of claim 28, furthercomprising a control circuit receiving digital data as input andproviding said first and second control signals for each of saiddrivers.